1. Field of the Invention
The present invention relates to data processing apparatuses and data processing methods.
2. Description of the Related Art
When processing image data in an image forming apparatus or the like, part of the processing is sometimes executed through software run by an integrated processor rather than through dedicated hardware. Executing the processing through software makes it possible to allot multiple functions to individual usage situations, and also makes the system as a whole flexible and adaptable, for adding additional functions and so on. Multiple processors are generally installed, and recent years have seen a trend toward increasing the number of processors even more. Using multiple processors makes it possible to execute multiple processes using a pipeline architecture and execute single processes in parallel.
Incidentally, software processes executed by integrated processors tend to require more time for processing than processes executed by dedicated hardware, which, in image forming apparatuses or the like, can easily result in bottlenecks in the processing time of the overall system. Therefore, there is a method, when multiple processors are installed, that divides a single piece of image data into regions and processes the resulting regions of the image data in parallel using the respective multiple processors. For example, Japanese Patent Laid-Open No. 2010-73210 (called “Patent Document 1” hereinafter) proposes a method in which JPEG compression and decompression are executed in parallel using multiple processors.
Typical processors currently in use have cache memories, and thus it is necessary to maintain cache coherence when multiple processors divide data into regions and output that data to a single common memory-type primary storage unit. Because the multiple processors each have individual data caches, transactions that maintain the coherence of the data between each cache line size are carried out. If the same cache line is read from/written to independently by multiple processors, there is the risk that other data will be mistakenly overwritten as a result of one of the writes. In response to this issue, there are methods for maintaining cache coherence, such as providing dedicated hardware as per Japanese Patent Laid-Open No. 08-185359 (called “Patent Document 2” hereinafter). If dedicated hardware is not provided, the system can guarantee that the same cache lines are not shared by multiple processors by matching the allocation of regions handled by the respective processors to the cache line size. Thus this method serves to maintain cache coherence.
In Patent Document 1, the output data is discrete, and there is no configuration for maintaining cache coherence.
Meanwhile, if a configuration such as that disclosed in Patent Document 2 is used in order to maintain cache coherence between caches for multiple processors, the number of transactions for maintaining the cache coherence will increase, which runs the risk of reducing the performance of the system as a whole.
Furthermore, if an attempt is made to maintain cache coherence by matching the allocation of regions handled by the respective processors to the cache line size, the data to be processed cannot be divided into units that are smaller than the cache line size. Thus, in a system having multiple processors, there will be processors that cannot handle parallel processing, which may make it difficult to achieve an increase in the processing speed corresponding to the number of processors.